1. Field of the Invention
The present invention relates generally to semiconductor fabrication and, more particularly, to a method for sidewall etching, a method for etching during filling of a trench, and a method for semiconductor structure fabrication by shallow trench isolation in which a trench feature is formed in a substrate.
2. Description of the Related Art
In the fabrication of semiconductor devices, integrated circuit structures are typically fabricated in the form of multi-layer, also known as multi-level structures. Beginning at the substrate layer or level, transistor devices having diffusion regions are formed over and into silicon substrates. In subsequent layers, interconnect metallization lines are patterned and electrically connected to the transistor devices to define the desired functional device. As is well known, patterned conductive layers are insulated from other conductive layers by dielectric materials such as silicon dioxide. The insulating layers essentially form a substrate layer or level in a multi-layer structure. As used herein, the term “substrate” includes both a base substrate such as a silicon semiconductor wafer, and any substrate layer or level of a multi-layer structure.
In the fabrication of features in and on the substrate, trenches are typically formed in one material, e.g., a silicon substrate, polycrystalline silicon, metal or a dielectric substrate layer or level, and then filled with another material. An exemplary process is shallow trench isolation (STI) in which trenches are formed to define an active area of a device such as a well, a transistor, a memory cell, etc. Trenches are formed in the substrate to isolate a region that may eventually be doped to define a device. The trenches are filled with another, and often a different, dielectric material or a metal as the structures are fabricated.
FIGS. 1A, 1B, and 1C illustrate a typical STI fabrication process. As shown in FIG. 1A, trenches 12 are formed in a substrate 10. For ease of illustration, substrate 10 in FIGS. 1A, 1B, and 1C is illustrated as a silicon substrate 10 such as a semiconductor wafer. As is known, fabrication in subsequent substrate levels or layers may or may not include all of the process steps illustrated and described herein, and depending on fabrication process utilized, may or may not include additional processing operations not illustrated or described herein.
Returning to FIG. 1A, a pad oxide layer 14 is formed over the substrate 10, and a nitride layer 16 is formed over the pad oxide layer 14. By way of example, nitride layer 16 might be a layer of SiN. Trenches 12 have been formed through the nitride layer 16 and the pad oxide layer 14, and into the substrate 10.
FIG. 1B shows a next process step of the STI fabrication process begun in FIG. 1A. In FIG. 1B, a liner 18 is shown in trenches 12. In some applications, the liner 18 is an oxide or other material grown inside the trench 12. Depending on the substrate, and the material, the liner 18 may or may not be used.
FIG. 1C shows a fill layer 20 deposited over the structure filling trenches 12 and covering nitride layer 16. The fill layer 20 is typically an oxide or metal, such as tetraethylorthosilicate (TEOS), oxide formed by using high density plasma (HDP), silicon dioxide, and the like, and may be deposited over the structure by chemical vapor deposition (CVD). Once the fabrication has reached the stage represented in FIG. 1C, processing continues to remove the fill layer 20, the nitride layer 16, and the pad oxide layer 14, leaving the trench 12 filled and prepared for continued structure fabrication.
A conventional technique for filling the trench 12 formed in substrate 10, e.g., the trench 12 formed in STI fabrication operations, includes CVD of a dielectric material or of a conductive material. Due to the topography of the trench 12, however, material deposited usually accumulates at the opening of the trench 12, inhibiting the filling. FIG. 2A shows a detail view of a substrate 10 having a trench 12 formed therein, and a partially-deposited fill layer 20. A liner 18 has been formed in trench 12, and fill layer 20 has been deposited to fill trench 12. As can be seen in FIG. 2A, deposition of fill layer 20 results in significant narrowing at trench opening 22. Continued deposition of fill layer 20 may or may not result in complete filling of trench 12, and to prevent incomplete filling of trench 12 and formation of unacceptable voids in the fill layer 20, additional processing to widen trench opening 22 is often required.
FIG. 2B illustrates the formation of a void 24 within the fill layer 20 in trench 12 if additional processing to widen trench opening 22 is not accomplished. Typically, a process such as dry etching is utilized to remove the material that narrows trench opening 22, so that filling can further proceed. However, when etching the material on the sidewall and trench opening 22, the material formed at the bottom of the trench 12 is inevitably removed as well. Therefore, dry etching is not an ideal method to enhance or facilitate the access to a formed trench and enable trench filling.
As process technology evolves, resulting in smaller features and more complex and dense semiconductor structures fabricated in and on substrates, trenches become smaller and narrower, and trench openings become increasingly susceptible to blockage during trench-filling processes. As is well known, voids in trench filling material are unacceptable. As such, a method of etching to be used in trench-filling processes that enables sufficient access for complete trench-filling without voids and without removal of desired material at the bottom of the trench is needed.